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Cadence links FPGA pin allocation to PCB-layout tools

Designers who use today’s large FPGAs on their PCB face an increasing problem handling the pin-out and board tracking around the packages of those programmable devices. The FPGAs have large, sometimes very large, pin-outs; they offer considerable flexibility in allocation of pins to internal logic functions, but also have complex rules that you must follow when doing so. The FPGA designer who does this, according to Cadence, typically does so today with minimal knowledge of the connectivity of those pins to other packages on the PCB. Another engineer will develop the overall circuit function, connecting the FPGA to processors, memory and other packages. The job of creating the board layout falls to yet another engineer, who has to find escape routes for all the signal groups that emerge from the FPGA and route them to other packages, while taking account of features such as wide memory buses and fast signal lines.

Designers who use today’s large FPGAs on their PCB face an increasing problem handling the pin-out and board tracking around the packages of those programmable devices. The FPGAs have large, sometimes very large, pin-outs; they offer considerable flexibility in allocation of pins to internal logic functions, but also have complex rules that you must follow when doing so. The FPGA designer who does this, according to Cadence, typically does so today with minimal knowledge of the connectivity of those pins to other packages on the PCB. Another engineer will develop the overall circuit function, connecting the FPGA to processors, memory and other packages. The job of creating the board layout falls to yet another engineer, who has to find escape routes for all the signal groups that emerge from the FPGA and route them to other packages, while taking account of features such as wide memory buses and fast signal lines.

Cadence has incorporated software from Taray into Allegro and OrCad that provides automated assistance in the FPGA pin-allocation design step, yielding a correct- by-construction process. Taray calls its process automated placement-aware FPGA pin I/O-assignment synthesis. The software has knowledge of the pin-allocation rules for Xilinx and Altera FPGAs, and of the connectivity of the logic function in the FPGAs to other packages. One of the problems that Shah identifi es about today’s process is that large FPGAs contain so much logic that it is diffi cult to represent their functions in an understandable form on a single diagram; so engineers view different functions on different pages and lose sight of the bigger picture. The Taray tool tracks that information; it also allows you to make a generic placement of packages on a “canvas” when carrying out initial PCB design, and it will yield a global view of connectivity and connection density. It further avoids the problem of manual errors in the pinallocation step—existing tools will trap some such errors, Shah says, but not all.

The offering is applicable, Cadence says, whether you are designing an FPGAbased board as a fi nal product or whether you are building an ASIC prototype in which the logic of the target device is divided amongst many complex FPGAs. Using the Taray/Allegro tool greatly simplifi es such designs, Shah says, because the process that fragments the logic on to the FPGAs has no knowledge of placement or layout; with the new software, you can automate pin assignment across all of the FPGAs in one step.

The ability to quickly view an optimised placement for any given logic architecture also permits you, Cadence explains, to explore cost/ performance trade-offs at the board-design level. Under the Cadence PCB tool brands, the software is available—for the version 16.2 release— as OrCAD FPGA System Planner or Allegro FPGA System Planner L, XL and GXL tiers, and it is tightly integrated with OrCAD Capture, OrCAD PCB Designer, Allegro Design Entry HDL and Allegro PCB Design products. Taray also continues to sell its tool offering, called 7Circuits, as a stand-alone product.

Cadence, www.cadence.com.
Taray, www.tarayinc.com